A real-time, scalable, fast and resource-efficient decoder for a quantum computer

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ABSTRACT The development of quantum computers will require the careful management of the noise effects associated with qubit performance. However, the decoders responsible for diagnosing


noise-induced computational errors must use resources efficiently to enable scaling to large qubit counts and cryogenic operation. They must also operate at speed, to avoid an exponential


slowdown in the logical clock rate of the quantum computer. To overcome these challenges, we introduce the Collision Clustering decoder and demonstrate its implementation on


field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) hardware. We simulate logical memory experiments using the leading quantum error correction scheme


(the surface code) and demonstrate megahertz decoding speed—matching the requirements of fast-operating modalities such as superconducting qubits—up to an 881 qubit surface code with the


FPGA and 1,057 qubit surface code with the ASIC. The ASIC design occupies 0.06 mm2 and consumes only 8 mW of power. Access through your institution Buy or subscribe This is a preview of


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ACCESS OPTIONS: * Log in * Learn about institutional subscriptions * Read our FAQs * Contact customer support SIMILAR CONTENT BEING VIEWED BY OTHERS QUANTUM ERROR CORRECTION BELOW THE


SURFACE CODE THRESHOLD Article Open access 09 December 2024 REALIZING REPEATED QUANTUM ERROR CORRECTION IN A DISTANCE-THREE SURFACE CODE Article 25 May 2022 OVERCOMING LEAKAGE IN QUANTUM


ERROR CORRECTION Article Open access 05 October 2023 DATA AVAILABILITY The stim32 circuits used to generate the samples and raw data from all the plots in this study are available via Zenodo


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references ACKNOWLEDGEMENTS We thank S. Brierley and J. Taylor for encouraging this research and related discussions. We also thank M. Maragkou and L. Martiradonna for feedback on the


manuscript. AUTHOR INFORMATION AUTHORS AND AFFILIATIONS * Riverlane, Cambridge, UK Ben Barber, Kenton M. Barnes, Tomasz Bialas, Okan Buğdaycı, Earl T. Campbell, Neil I. Gillespie, Kauser


Johar, Ram Rajan, Adam W. Richardson, Luka Skoric, Canberk Topal, Mark L. Turner & Abbas B. Ziad * Department of Physics and Astronomy, University of Sheffield, Sheffield, UK Earl T.


Campbell Authors * Ben Barber View author publications You can also search for this author inPubMed Google Scholar * Kenton M. Barnes View author publications You can also search for this


author inPubMed Google Scholar * Tomasz Bialas View author publications You can also search for this author inPubMed Google Scholar * Okan Buğdaycı View author publications You can also


search for this author inPubMed Google Scholar * Earl T. Campbell View author publications You can also search for this author inPubMed Google Scholar * Neil I. Gillespie View author


publications You can also search for this author inPubMed Google Scholar * Kauser Johar View author publications You can also search for this author inPubMed Google Scholar * Ram Rajan View


author publications You can also search for this author inPubMed Google Scholar * Adam W. Richardson View author publications You can also search for this author inPubMed Google Scholar *


Luka Skoric View author publications You can also search for this author inPubMed Google Scholar * Canberk Topal View author publications You can also search for this author inPubMed Google


Scholar * Mark L. Turner View author publications You can also search for this author inPubMed Google Scholar * Abbas B. Ziad View author publications You can also search for this author


inPubMed Google Scholar CONTRIBUTIONS K.M.B., N.I.G., K.J. and L.S. led the direction of the project with E.T.C. and B.B. providing guidance and advice. K.M.B., K.J. and L.S. developed the


algorithm. K.M.B., K.J., A.W.R., L.S., M.L.T. and A.B.Z. developed software tools necessary to model the algorithm and its implementation on hardware. K.J. led T.B., O.B., R.R. and C.T. with


the development of the hardware implementation of the decoder on the FPGA and ASIC, and the collection of the resulting data. L.S. analysed the data for both the hardware decoder and


software models. K.M.B., T.B., N.I.G., K.J. and L.S. wrote an initial draft of the article. N.I.G. and L.S. wrote the final version of the article. CORRESPONDING AUTHORS Correspondence to


Neil I. Gillespie or Luka Skoric. ETHICS DECLARATIONS COMPETING INTERESTS The authors declare no competing interests. PEER REVIEW PEER REVIEW INFORMATION _Nature Electronics_ thanks Blake


Johnson and the other, anonymous, reviewer(s) for their contribution to the peer review of this work. ADDITIONAL INFORMATION PUBLISHER’S NOTE Springer Nature remains neutral with regard to


jurisdictional claims in published maps and institutional affiliations. SUPPLEMENTARY INFORMATION SUPPLEMENTARY INFORMATION Supplementary Figs. 1–3 and Discussion. RIGHTS AND PERMISSIONS


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CITE THIS ARTICLE Barber, B., Barnes, K.M., Bialas, T. _et al._ A real-time, scalable, fast and resource-efficient decoder for a quantum computer. _Nat Electron_ 8, 84–91 (2025).


https://doi.org/10.1038/s41928-024-01319-5 Download citation * Received: 22 February 2024 * Accepted: 21 November 2024 * Published: 07 January 2025 * Issue Date: January 2025 * DOI:


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